Pipelined read-modify-write operations in cache memory
US11609818B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2022 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Jan 31, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/608
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.