Inventor · Dallas, TX, US

Daniel Wu

46Patents
4h-index
33Co-inventors
63Inventor score

Filing activity: Aug 10, 2000 → Mar 8, 2024

Most-cited inventions

PatentTitleAreaCited byStatus
US9606803B2 Highly integrated scalable, flexible DSP megamodule architecture Electricity 75 Active
US9152586B2 Coherent cache system with optional acknowledgement for out-of-order coherence transaction completion Physics 29 Active
US10162641B2 Highly integrated scalable, flexible DSP megamodule architecture Electricity 8 Active
US11237905B2 Pipelined read-modify-write operations in cache memory Physics 5 Active
US6829739B1 Apparatus and method for data buffering Physics 4 Expired
US10802974B2 Virtual network pre-arbitration for deadlock avoidance and enhanced performance Physics 4 Active
US11036648B2 Highly integrated scalable, flexible DSP megamodule architecture Electricity 3 Active
US11487442B1 Data storage interface for protocol-agnostic storage services Electricity 3 Active
US9208120B2 Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Emerging Cross-Sectional Technologies 2 Active
US9489307B2 Multi domain bridge with auto snoop response Physics 2 Active
US11487616B2 Write control for read-modify-write operations in cache memory Physics 2 Active
US10599433B2 Cache management operations using streaming engine Physics 1 Active
US11347644B2 Distributed error detection and correction with hamming code handoff Physics 1 Active
US10606596B2 Cache preload operations using streaming engine Physics 1 Active
US11609818B2 Pipelined read-modify-write operations in cache memory Physics 1 Active
US12210454B1 Data storage interface layer with access and transformation management Physics 0 Active
US12072812B2 Highly integrated scalable, flexible DSP megamodule architecture Electricity 0 Active
US12314187B2 Software-hardware memory management modes Physics 0 Active
US12430201B2 Multi-processor bridge with cache allocate awareness Physics 0 Active
US11853225B2 Software-hardware memory management modes Physics 0 Active
US9465767B2 Multi-processor, multi-domain, multi-protocol cache coherent speculation aware shared memory controller and interconnect Emerging Cross-Sectional Technologies 0 Active
US11429526B2 Credit aware central arbitration for multi-endpoint, multi-core system Physics 0 Active
US12079471B2 Adaptive credit-based replenishment threshold used for transaction arbitration in a system that supports multiple levels of credit expenditure Physics 0 Active
US10990529B2 Multi-power-domain bridge with prefetch and write merging Physics 0 Active
US9465741B2 Multi processor multi domain conversion bridge with out of order return buffering Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.