Scalable scribe regions for implementing user circuit designs in an integrated circuit using dynamic function exchange
US11610042B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 28, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Oct 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Using scalable scribe regions for implementing a user circuit design includes generating a scribe region having a plurality of contours for a static top design of a circuit design for an integrated circuit. The static top design is configured to integrate with a user circuit design in the integrated circuit. Each contour defines a different size of the scribe region having a boundary that extends outward in at least one direction from a boundary of a floorplan area of the static top design on the IC. The scribe region can be translated into design constraints defining the plurality of contours of the scribe region and restrict placement of components of the user circuit design within the scribe region as sized according to a selected contour. The static top design and the plurality of design constraints can be stored in a memory for use in implementing the user circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.