Well tap for an integrated circuit product and methods of forming such a well tap
US11610843B2 · kind B2 · utility
0Cited by
2References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Mar 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/485
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.