Chip packaging method and package structure
US11610855B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 2, 2020 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Mar 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides a chip packaging method and a package structure. The chip packaging method comprises: forming a wafer conductive layer on a wafer active surface of a wafer; forming a protective layer having certain material properties on the wafer conductive layer, the protective layer encapsulating the wafer conductive layer and exposing a front surface of the wafer conductive layer; separating (such as cutting) the wafer formed with the wafer conductive layer and the protective layer to form a die; attaching (such as adhering) the die onto a carrier; forming a molding layer having certain material properties on a die back surface of the die on the carrier; removing (such as stripping off) the carrier; forming a panel-level conductive layer electrically connected with the wafer conductive layer; and forming a dielectric layer. The package structure has a series of structural and material properties, so as to reduce warpage in the packaging process, lower a requirement on an accuracy of aligning the die, reduce a difficulty in the packaging process, and make the packaged chip more durable, and thus the present disclosure is especially suitable for large panel-level …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.