Patent · US Active

Semiconductor packages with chiplets coupled to a memory device

US11610862B2 · kind B2 · utility

0Cited by
1References
24Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 28, 2018
Grant dateMar 21, 2023
Priority date—
Expiry dateJul 21, 2041

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/15313
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.