Coherence protocol for hardware transactional memory in shared memory using non volatile memory with log and no lock
US11614959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 17, 2018 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention relates to a data processing system and a date processing method. The data processing system is configured to perform a hardware transactional memory (HTM) transaction. The data processing system comprises a byte-addressable nonvolatile memory for persistently storing data and a processor being configured to execute an atomic HTM write operation in connection with committing the HTM transaction by writing an indicator to the nonvolatile memory indicating the successful commit of the HTM transaction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.