Semiconductor FinFET device and method
US11615965B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Sep 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.