Semiconductor device having alignment pads and method of manufacturing the same
US11616032B2 · kind B2 · utility
0Cited by
3References
28Claims
0Family size
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Key dates
| Filing date | Jan 20, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Apr 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/05193
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor substrate having a main surface over which a plurality of die pads and at least one alignment pad for optical process control for semiconductor wafer probing are arranged. The alignment pad has a hardness smaller than a hardness of the plurality of die pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.