Underfill structure for semiconductor packages and methods of forming the same
US11621205B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Apr 1, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an underfill structure and semiconductor packages including the underfill structure are disclosed. In an embodiment, the semiconductor package may include a package including an integrated circuit die; an interposer bonded to the integrated circuit die by a plurality of die connectors; and an encapsulant surrounding the integrated circuit die. The semiconductor package may further include a package substrate bonded to the interposer by a plurality of conductive connectors; a first underfill between the package and the package substrate, the first underfill having a first coefficient of thermal expansion (CTE); and a second underfill surrounding the first underfill, the second underfill having a second CTE less than the first CTE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.