Method and apparatus for through silicon die level interconnect
US11621219B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2021 |
| Grant date | Apr 4, 2023 |
| Priority date | — |
| Expiry date | Jun 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/10158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic assembly is disclosed. The electronic assembly includes a primary die, comprising a bulk layer, an integrated circuitry layer, a metal layer, a first redistribution layer, and a first attachment layer. The primary die further includes at least one aligned through-hole in the bulk layer and integrated circuitry layer. The electronic assembly further includes a secondary die physically coupled to the primary die via a second attachment layer. The electronic assembly further includes an interconnect header that includes plurality of interconnect filaments configured to electrically couple the first redistribution layer to one of the at least one metal layer via the at least one bulk layer through-hole and the at least one integrated circuitry through-hole. The interconnect header is generated by applying an electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking and attaching the wafers into a wafer stack, and dicing the wafer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.