Multilevel memory stack structure with tapered inter-tier joint region and methods of making thereof

US11621277B2 · kind B2 · utility

Assignee

• Sandisk Technologies, Inc. · US

Inventors

• Monica Titus · Santa Clara, US
• Zhixin Cui · Yokkaichi, JP
• Senaka Kanakamedala · San Jose, US
• Yao-Sheng Lee · Tampa, US
• Chih-Yu Lee · Yokkaichi, JP

Key dates

• Filing date: Nov 16, 2020
• Grant date: Apr 4, 2023
• Expiry date: Jun 17, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/50

Abstract

A joint level dielectric material layer is formed over a first alternating stack of first insulating layers and first spacer material layers. A first memory opening is formed with a tapered sidewall of the joint level dielectric material layer. A second alternating stack of second insulating layers and second spacer material layers is formed over the joint level dielectric material layer. An inter-tier memory opening is formed, which includes a volume of an second memory opening that extends through the second alternating stack and a volume of the first memory opening. A memory film and a semiconductor channel are formed in the inter-tier memory opening with respective tapered portions overlying the tapered sidewall of the joint level dielectric material layer.