Technologies for controlling memory access transactions received from one or more I/O devices
US11625275B2 · kind B2 · utility
0Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2020 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Dec 31, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W12/48
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technologies for secure I/O include a compute device, which further includes a processor, a memory, a trusted execution environment (TEE), one or more input/output (I/O) devices, and an I/O subsystem. The I/O subsystem includes a device memory access table (DMAT) programmed by the TEE to establish bindings between the TEE and one or more I/O devices that the TEE trusts and a memory ownership table (MOT) programmed by the TEE when a memory page is allocated to the TEE.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.