Wear leveling in EEPROM emulator formed of flash memory cells
US11626176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2022 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Jan 7, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2263
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments relate to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. The embodiments comprise a system and method for receiving an erase command and a logical address, the logical address corresponding to a sector of physical words of non-volatile memory cells in an array of non-volatile memory cells, the sector comprising a first physical word, a last physical word, and one or more physical words between the first physical word and the last physical word; when a current word, identified by an index bit, is the last physical word in the sector, erasing the sector; and when the current word is not the last physical word in the sector, changing a next index bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.