Packetized power-on-self-test controller for built-in self-test
US11626178B2 · kind B2 · utility
0Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Sep 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3602
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.