Machine learning on overlay management
US11626304B2 · kind B2 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Feb 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05B2219/45031
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
The current disclosure describes techniques for managing vertical alignment or overlay in semiconductor manufacturing using machine learning. Alignments of interconnection features in a fan-out WLP process are evaluated and managed through the disclosed techniques. Big data and neural networks system are used to correlate the overlay error source factors with overlay metrology categories. The overlay error source factors include tool related overlay source factors, wafer or die related overlay source factors and processing context related overlay error source factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.