Package comprising a solder resist layer configured as a seating plane for a device
US11626336B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 2019 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Oct 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A package that includes a substrate having a first surface; a solder resist layer coupled to the first surface of the substrate; a device located over the solder resist layer such that a portion of the device touches the solder resist layer; and an encapsulation layer located over the solder resist layer such that the encapsulation layer encapsulates the device. The solder resist layer is configured as a seating plane for the device. The device is located over the solder resist layer such that a surface of the device facing the substrate is approximately parallel to the first surface of the substrate. The solder resist layer includes at least one notch. The device is located over the solder resist layer such that at least one corner of the device touches the at least one notch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.