Co-integrated vertically structured capacitive element and fabrication process
US11626365B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 9, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Oct 14, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
First and second wells are formed in a semiconductor substrate. First and second trenches in the first second wells, respectively, each extend vertically and include a central conductor insulated by a first insulating layer. A second insulating layer is formed on a top surface of the semiconductor substrate. The second insulating layer is selectively thinned over the second trench. A polysilicon layer is deposited on the second insulating layer and then lithographically patterned to form: a first polysilicon portion over the first well that is electrically connected to the central conductor of the first trench to form a first capacitor plate, a second capacitor plate formed by the first well; and a second polysilicon portion over the second well forming a floating gate electrode of a floating gate transistor of a memory cell having an access transistor whose control gate is formed by the central conductor of the second trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.