Memory device and hybrid spacer thereof
US11626412B2 · kind B2 · utility
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14Claims
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Assignee
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Key dates
| Filing date | Dec 3, 2021 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device includes forming a metal layer and a spacer adjacent to the metal layer. The spacer includes a composite-dielectric layer including a composite-dielectric material. A composition of the composite-dielectric material is a mixture of a composition of a first dielectric material and a composition of a second dielectric material different from the first dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.