Memory arrays and methods used in forming a memory array comprising strings of memory cells

US11626423B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Xiaosong Zhang · Boise, US
• Yi Hu · Boise, US
• Tom J. John · Boise, US
• Wei Yeeng Ng · Boise, US
• Chandra S. Tiwari · Boise, US

Key dates

• Filing date: Jul 12, 2021
• Grant date: Apr 11, 2023
• Expiry date: Sep 21, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/10
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In some embodiments, a memory array comprising strings of memory cells comprise laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Insulative pillars are laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The pillars comprise vertically-spaced and radially-projecting insulative rings in the conductive tiers as compared to the insulative tiers. Other embodiments, including methods, are disclosed.