Efficient fabrication of memory structures
US11626452B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2020 |
| Grant date | Apr 11, 2023 |
| Priority date | — |
| Expiry date | Feb 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
Abstract
Methods, systems, and devices for efficient fabrication of memory structures are described. A multi-deck memory device may be fabricated using a sequence of fabrication steps that include depositing a first metal layer, depositing a cell layer on the first metal layer to form memory cells of the first memory deck, and depositing a second metal layer on the cell layer. The second metal layer may be deposited using a single deposition process rather than using multiple deposition processes. A second memory deck may be formed on the second metal layer such that stacked memory cells from the first and second deck share the use of the second metal layer. Using a single deposition process for the second metal layer may decrease the quantity of fabrication steps used to fabricate the multi-deck memory array and reduce or eliminate the exposure of the cell material to metal etchants.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.