Systems and methods for reading and writing sparse data in a neural network accelerator
US11630770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2019 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Jun 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed herein includes a system, a method, and a device for reading and writing sparse data in a neural network accelerator. A plurality of slices can be established to access a memory having an access size of a data word. A first slice can be configured to access a first side of the data word in memory. Circuitry can access a mask identifying byte positions within the data word having non-zero values. The circuitry can modify the data word to have non-zero byte values stored starting at an end of the first side, and any zero byte values stored in a remainder of the data word. A determination can be made whether a number of non-zero byte values is less than or equal to a first access size of the first slice. The circuitry can write the modified data word to the memory via at least the first slice.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.