Liangzhen Lai
15Patents
2h-index
11Co-inventors
43Inventor score
Filing activity: Mar 23, 2016 → Mar 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11709783B1 | Tensor data distribution using grid direct-memory access (DMA) controller | Physics | 8 | Active |
| US11301545B2 | Power efficient multiply-accumulate circuitry | Physics | 2 | Active |
| US11704562B1 | Architecture for virtual instructions | Physics | 2 | Active |
| US12001893B1 | Distributed synchronization scheme | Physics | 1 | Active |
| US11698529B2 | Systems and methods for distributing a neural network across multiple computing devices | Physics | 1 | Active |
| US12197362B2 | Batch matrix multiplication operations in a machine learning accelerator | Physics | 0 | Active |
| US10977002B2 | System and method for supporting alternate number format for efficient multiplication | Physics | 0 | Active |
| US11675998B2 | System and method for performing small channel count convolutions in energy-efficient input operand stationary accelerator | Emerging Cross-Sectional Technologies | 0 | Active |
| US11954025B2 | Systems and methods for reading and writing sparse data in a neural network accelerator | Physics | 0 | Active |
| US11385864B2 | Counter based multiply-and-accumulate circuit for neural network | Physics | 0 | Active |
| US9922152B2 | Computer implemented system and method for reducing failure in time soft errors of a circuit design | Physics | 0 | Active |
| US11972349B1 | Flexible compute array utilization in a tensor processor | Physics | 0 | Active |
| US12265492B2 | Circular buffer for input and output of tensor computations | Physics | 0 | Active |
| US11630770B2 | Systems and methods for reading and writing sparse data in a neural network accelerator | Physics | 0 | Active |
| US10122384B2 | Logical interleaver | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.