Clock generation for timing communications with ranks of memory devices
US11630788B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2020 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Apr 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.