Ian Shaeffer
234Patents
16h-index
67Co-inventors
89Inventor score
Filing activity: Apr 29, 2000 → May 31, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7562271B2 | Memory system topologies including a buffer device and an integrated circuit memory device | Electricity | 52 | Active |
| US8352805B2 | Memory error detection | Electricity | 41 | Active |
| US7836378B2 | System to detect and identify errors in control information, read data and/or write data | Physics | 33 | Active |
| US8344475B2 | Integrated circuit heating to effect in-situ annealing | Electricity | 32 | Active |
| US8555116B1 | Memory error detection | Electricity | 30 | Active |
| US7486104B2 | Integrated circuit with graduated on-die termination | Electricity | 29 | Active |
| US7321524B2 | Memory controller with staggered request signal output | Physics | 27 | Expired |
| US9117496B2 | Memory device comprising programmable command-and-address and/or data interfaces | Electricity | 26 | Active |
| US8108607B2 | Memory system topologies including a buffer device and an integrated circuit memory device | Electricity | 24 | Active |
| US8504788B2 | Memory controller, system and method for read signal timing calibration | Physics | 24 | Active |
| US8380943B2 | Variable-width memory module and buffer | Physics | 21 | Active |
| US7729151B2 | System including a buffered memory module | Electricity | 19 | Active |
| US7685364B2 | Memory system topologies including a buffer device and an integrated circuit memory device | Electricity | 17 | Active |
| US8407441B2 | Method and apparatus for calibrating write timing in a memory system | Physics | 16 | Active |
| US9330735B2 | Memory with deferred fractional row activation | Physics | 16 | Active |
| US10381067B2 | Memory system topologies including a buffer device and an integrated circuit memory device | Electricity | 16 | Active |
| US8089824B2 | Memory controller with staggered request signal output | Physics | 15 | Active |
| US6460170B1 | Connection block for interfacing a plurality of printed circuit boards | Electricity | 15 | Expired |
| US9025409B2 | Memory buffers and modules supporting dynamic point-to-point connections | Emerging Cross-Sectional Technologies | 14 | Active |
| US9268719B2 | Memory signal buffers and modules supporting variable access granularity | Emerging Cross-Sectional Technologies | 14 | Active |
| US9007862B2 | Reducing memory refresh exit time | Physics | 13 | Active |
| US9037949B1 | Error correction in a memory device | Physics | 13 | Active |
| US9489323B2 | Folded memory modules | Emerging Cross-Sectional Technologies | 13 | Active |
| US7558150B2 | Memory controller with staggered request signal output | Physics | 13 | Active |
| US8707110B1 | Memory error detection | Electricity | 13 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.