Serial peripheral interface (SPI) automatic register address incrementation across data frames

US11630796B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Andreas Jansen · Rosenheim, DE
• Richard Heinz · Munich, DE
• Catalina-Petruta Juglan · Bucharest, RO
• Stephan LEISENHEIMER · Deisenhofen, DE
• Lacramioara Mihaela Smochina · Roman, RO

Key dates

• Filing date: May 7, 2021
• Grant date: Apr 18, 2023
• Expiry date: May 7, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/4022
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A serial peripheral interface (SPI) communication system includes a memory configured with a start register address and an end register address that define a register address range for a data operation; a chip select terminal configured to receive a chip select signal comprising an active and idle signal levels that define a plurality of chip select frames; a serial data input terminal configured to receive a master out, slave in (MOSI) signal, wherein the MOSI signal includes configuration information received in a first chip select frame of the data operation, wherein the configuration information includes an operation command bit indicating whether the data operation is a write operation or a read out operation and an auto-incrementation control bit indicating whether automatic register address incrementation across chip select frames is enabled or disabled; and a serial data output terminal configured to transmit a master in, slave out (MISO) signal.