Memory circuit and manufacturing method thereof
US11631447B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | Jul 25, 2019 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Jul 25, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a memory cell and a source line transistor. The memory cell includes a first transistor, a second transistor, a third transistor, and a fourth transistor. The second transistor and the third transistor form an inverter electrically connected to a drain of the first transistor. The inverter is configured to store two states with different applied voltages. The fourth transistor is electrically connected to a node of the inverter. The source line transistor is electrically connected to the fourth transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.