Enable control circuit and semiconductor memory
US11632113B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2022 |
| Grant date | Apr 18, 2023 |
| Priority date | — |
| Expiry date | Feb 9, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/58
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An enable control circuit, which includes a counter circuit configured to count a current clock cycle and determine a clock cycle count value; a selection circuit configured to determine a clock cycle count target value according to a first setting signal; and a control circuit configured to control an ODT path to be enabled and start the counter circuit when the voltage level of an ODT pin signal is flipped over, control the ODT path to be switched from being enabled to disabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal is not changed, and control the ODT path continue to be enabled when the clock cycle count value reaches the clock cycle count target value and the voltage level of the ODT pin signal flips again.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.