Scalable sparse matrix multiply acceleration using systolic arrays with feedback inputs

US11636174B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Subramaniam Maiyuran · Citrus, US
• Jorge Parra · Cameron Park, US
• Supratim Pal · Bengaluru, IN
• Ashutosh Garg · Sunnyvale, US
• Shubra Marwaha · Folsom, US
• Chandra Gurram · Folsom, US
• Darin Starkey · Roseville, US
• Durgesh Borkar · Folsom, US
• Varghese George · Folsom, US

Key dates

• Filing date: Nov 16, 2021
• Grant date: Apr 25, 2023
• Expiry date: Nov 16, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06N3/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.