Uniform via pad structure having covered traces between partially covered pads
US11637057B2 · kind B2 · utility
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8Claims
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Key dates
| Filing date | Dec 21, 2019 |
| Grant date | Apr 25, 2023 |
| Priority date | — |
| Expiry date | Dec 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/486
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.