Unit element for performing multiply-accumulate operations
US11640196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4814
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.