Error rates for memory with built in error correction and detection
US11640334B2 · kind B2 · utility
0Cited by
1References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 21, 2021 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | May 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/108
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The methods and systems improve uncorrectable error (UE) and silent data corruption (SDC) rates for memory chips and improve error correction of the memory chips. The systems may include a memory bank with a plurality of memory chips in communication with a memory controller. The memory bank may use one additional memory chip that stores a bitwise parity of the data stored in the remaining memory chips of the memory bank. The parity bits are used to rebuild corrupted data when a UE occurs. The parity bits are also used to detect whether a SDC occurred in the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.