Shared memory mesh for switching
US11641326B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2019 |
| Grant date | May 2, 2023 |
| Priority date | — |
| Expiry date | Aug 23, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Examples are described herein that relate to a mesh in a switch fabric. The mesh can include one or more buses that permit operations (e.g., read, write, or responses) to continue in the same direction, drop off to a memory, drop off a bus to permit another operation to use the bus, or receive operations that are changing direction. A latency estimate can be determined at least for operations that drop off from a bus to permit another operation to use the bus or receive and channel operations that are changing direction. An operation with a highest latency estimate (e.g., time of traversing a mesh) can be permitted to use the bus, even causing another operation, that is not to change direction, to drop off the bus and re-enter later.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.