James E. McCormick, Jr.
16Patents
6h-index
21Co-inventors
66Inventor score
Filing activity: Feb 18, 2000 → Aug 23, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6721875B1 | Method and apparatus for implementing a single-syllable IP-relative branch instruction and a long IP-relative branch instruction in a processor which fetches instructions in bundle form | Physics | 52 | Expired |
| US6351796B1 | Methods and apparatus for increasing the efficiency of a higher level cache by selectively performing writes to the higher level cache | Physics | 24 | Expired |
| US6678817B1 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Physics | 13 | Expired |
| US8443171B2 | Run-time updating of prediction hint instructions | Physics | 13 | Active |
| US6629167B1 | Pipeline decoupling buffer for handling early data and late data | Physics | 11 | Expired |
| US6470438B1 | Methods and apparatus for reducing false hits in a non-tagged, n-way cache | Physics | 7 | Expired |
| US6647487B1 | Apparatus and method for shift register rate control of microprocessor instruction prefetches | Physics | 6 | Expired |
| US6516388B1 | Method and apparatus for reducing cache pollution | Physics | 5 | Expired |
| US7747844B2 | Acquiring instruction addresses associated with performance monitoring events | Physics | 4 | Active |
| US10346177B2 | Boot process with parallel memory initialization | Physics | 3 | Active |
| US9442861B2 | System and method for out-of-order prefetch instructions in an in-order pipeline | Physics | 2 | Active |
| US6622209B2 | Use of non-count data and index hashing to reduce false hits in a non-tagged, n-way cache | Physics | 2 | Expired |
| US11641326B2 | Shared memory mesh for switching | Electricity | 1 | Active |
| US10261909B2 | Speculative cache modification | Emerging Cross-Sectional Technologies | 0 | Active |
| US9092346B2 | Speculative cache modification | Emerging Cross-Sectional Technologies | 0 | Active |
| US7356674B2 | Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine | Physics | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.