Method for identifying PCB core-layer properties
US11644501B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 21, 2020 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Sep 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/162
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A reference via in a set of plated vias on a printed circuit board is located. A reference lead is applied to the reference via. A test via in the set of plated vias is located. A test lead is applied to the test via. An electrical conductance between the reference via and the test via is measured. A property of a core layer of the printed circuit board is identified based on the electrical conductance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.