Efficient selection of a particular processor thread for handling an interrupt
US11645215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2021 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Aug 28, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/542
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A plurality of virtual processor threads are executed on the plurality of physical processor threads. In a data structure, information pertaining to a plurality of interrupt sources in the data processing system is maintained. The information includes a historical scope of transmission of interrupt commands for an interrupt source. Based on an interrupt request from an interrupt source, an interrupt master transmits a first interrupt bus command on an interconnect fabric of the data processing system to poll one or more interrupt snoopers regarding availability of one or more of the virtual processor threads to service an interrupt. The interrupt master updates the scope of transmission specified in the data structure based on a combined response to the first interrupt bus command. The interrupt master applies the scope of transmission specified in the data structure to a subsequent second interrupt bus command for the interrupt source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.