Machine learning based delay estimation
US11645440B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 2, 2020 |
| Grant date | May 9, 2023 |
| Priority date | — |
| Expiry date | Dec 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Training of a machine learning model used to infer estimated delays of circuit routes during placement and routing of a circuit design. Training can include selecting sample pairs of source pins and destination pins of an integrated circuit (IC) device, and determining respective delays of shortest paths that connect the source pins to the destination pins of the sample pairs based on a resistance-capacitance model of wires that form the shortest paths on the IC device. Respective sets of features are determined for the shortest paths, and the model is trained using the respective sets of features and the respective delays as labels. The machine learning model can be provided to an electronic design automation tool for estimating delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.