Patent · US Active

Integrating and accessing passive components in wafer-level packages

US11646288B2 · kind B2 · utility

0Cited by

1References

19Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Gianni SIGNORINI · Garching bei München, DE
Veronica Sciriha · Munich, DE
Thomas Wagner · Regelsbach, DE

Key dates

Filing date	Sep 29, 2017
Grant date	May 9, 2023
Priority date	—
Expiry date	Dec 1, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/19105
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In accordance with disclosed embodiments, there is a method of integrating and accessing passive components in three-dimensional fan-out wafer-level packages. One example is a microelectronic die package that includes a die, a package substrate attached to the die on one side of the die and configured to be connected to a system board, a plurality of passive devices over a second side of the die, and a plurality of passive device contacts over a respective passive die, the contacts being configured to be coupled to a second die mounted over the passive devices and over the second side of the die.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.