System and method to implement masked vector instructions
US11650817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2019 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Sep 18, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30134
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a register file comprising a length register, a vector register file comprising a plurality of vector registers, a mask register file comprising a plurality of mask registers, and a vector instruction execution circuit to execute a masked vector instruction comprising a first length register identifier representing the length register, a first vector register identifier representing a first vector register of the vector register file, and a first mask register identifier representing a first mask register of the mask register file, wherein the length register is to store a length value representing a number of operations to be applied to data elements stored in the first vector register, the first mask register is to store a plurality of mask bits, and a first mask bit of the plurality of mask bits determines whether a corresponding first one of the operations causes an effect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.