Method of certifying safety levels of semiconductor memories in integrated circuits
US11651134B2 · kind B2 · utility
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26References
20Claims
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Key dates
| Filing date | May 28, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jul 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.