Redundancy analysis circuit and memory system including the same
US11651831B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jul 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.