Via-trace structures
US11652036B2 · kind B2 · utility
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9References
19Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 2, 2018 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/73204
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are via-trace structures with improved alignment, and related package substrates, packages, and computing device. For example, in some embodiments, a package substrate may include a conductive trace, and a conductive via in contact with the conductive trace. The alignment offset between the conductive trace and the conductive via may be less than 10 microns, and conductive trace may have a bell-shaped cross-section or the conductive via may have a flared shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.