Semiconductor package
US11652066B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 3, 2021 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Sep 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor package includes forming an encapsulant covering at least a portion of each of an inactive surface and side surface of a semiconductor chip, the semiconductor chip having an active surface on which a connection pad is disposed and the inactive surface opposing the active surface; forming a connection structure having a first region and a second region sequentially disposed on the active surface of the semiconductor chip, and the connection structure including a plurality of redistribution layers electrically connected to the connection pad of the semiconductor chip and further including a ground pattern layer; and forming a metal layer disposed on an upper surface of the encapsulant, and extending from the upper surface of the encapsulant to a side surface of the first region of the connection structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.