Asymmetric junctions of high voltage transistor in NAND flash memory
US11653496B2 · kind B2 · utility
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15Claims
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Key dates
| Filing date | Sep 25, 2020 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jul 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/49
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.