Memory device with improved data retention
US11653498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | Jul 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.