Resistive 3D memory
US11653506B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2019 |
| Grant date | May 16, 2023 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device is provided with a support and several superimposed levels of resistive memory cells formed on the support, each level having one or more rows of one or more resistive memory cell(s), each resistive memory cell having a variable resistance memory element formed by an area of variable resistivity material arranged between a first electrode and a second electrode. The memory element is connected to a source region or drain region of a control transistor, the control transistor being formed in a given semiconductor layer of a stack of semiconductor layers formed on the support and wherein respective channel regions of respective control transistors of resist memory cells are arranged.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.