Preemptive read verification after hardware write back
US11656938B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Aug 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/81
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing device in a memory sub-system receives an indication that a write back operation was performed for a management unit in a memory device. Responsive to receiving the indication that the write back operation was performed, the processing device initiates a read verify operation for the management unit and receives an indication of a number of write back errors associated with the management unit during the read verify operation. The processing device further determines whether the number of write back errors satisfies a read verify threshold criterion, and responsive to the number of write back errors satisfying the read verify threshold criterion, remaps the management unit to a different location on the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.