Silicon over insulator two-transistor one-resistor in-series resistive memory cell
US11659720B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | May 23, 2023 |
| Priority date | — |
| Expiry date | Nov 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory (ReRAM) array is provided. The ReRAM array includes a silicon over insulator (SOI) substrate; a first bit line; a first inverted bit line of the first bit line; a second bit line; a second inverted bit line of the second bit line; a first word line; a first inverted word line of the first word line; a first ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element; and a second ReRAM cell comprising a first MOSFET, a second MOSFET, and a resistive element connected in series; wherein upon applying a predefined potential on elements of the first ReRAM cell, a state of the first ReRAM cell is adjusted without effecting a state of the second ReRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.