Managing memory device with processor-in-memory circuit to perform memory or processing operation
US11663008B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 2020 |
| Grant date | May 30, 2023 |
| Priority date | — |
| Expiry date | Mar 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory having a memory bank, a processor in memory (PIM) circuit, and control logic. The PIM circuit includes instruction memory storing at least one instruction provided from a host. The PIM circuit is configured to process an operation using data provided by the host or data read from the memory bank and to store at least one instruction provided by the host. The control logic is configured to decode a command/address received from the host to generate a decoding result and to perform a control operation so that one of i) a memory operation on the memory bank is performed and ii) the PIM circuit performs a processing operation, based on the decoding result. A counting value of a program counter instructing a position of the instruction memory is controlled in response to the command/address instructing the processing operation be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.