Hak-Soo Yu
63Patents
9h-index
70Co-inventors
81Inventor score
Filing activity: Oct 8, 1997 → Jul 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8619490B2 | Semiconductor memory devices | Physics | 175 | Active |
| US6091663A | Synchronous burst semiconductor memory device with parallel input/output data strobe clocks | Physics | 27 | Expired |
| US9053813B2 | Method and apparatus for refreshing and data scrubbing memory device | Physics | 24 | Active |
| US6366149B1 | Delay circuit having variable slope control and threshold detect | Electricity | 20 | Expired |
| US5991233A | Switch signal generators for simultaneously setting input/output data paths, and high-speed synchronous SRAM devices using the same | Physics | 13 | Expired |
| US9600362B2 | Method and apparatus for refreshing and data scrubbing memory device | Physics | 12 | Active |
| US9058897B2 | Semiconductor memory device storing memory characteristic information, memory module and memory system having the same, and operating method thereof | Physics | 11 | Active |
| US6166969A | Method and apparatus for a level shifter for use in a semiconductor memory device | Electricity | 11 | Expired |
| US6128233A | Data transmission circuitry of a synchronous semiconductor memory device | Physics | 10 | Expired |
| US10592467B2 | Semiconductor memory device and method of operating a semiconductor device in a processor mode or a normal mode | Physics | 9 | Active |
| US8553445B2 | Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same | Physics | 9 | Active |
| US6147913A | Data transmission circuitry of a synchronous semiconductor memory device | Physics | 9 | Expired |
| US8934311B2 | Semiconductor memory device capable of screening a weak bit and repairing the same | Physics | 9 | Active |
| US8553484B2 | Semiconductor memory device for data sensing | Physics | 8 | Active |
| US7616512B2 | Semiconductor memory device with hierarchical bit line structure | Physics | 8 | Active |
| US9335951B2 | Memory device for reducing a write fail, a system including the same, and a method thereof | Emerging Cross-Sectional Technologies | 8 | Active |
| US8987811B2 | Semiconductor devices including a vertical channel transistor and methods of fabricating the same | Electricity | 8 | Active |
| US9558805B2 | Memory modules and memory systems | Physics | 8 | Active |
| US7489570B2 | Semiconductor memory device with hierarchical bit line structure | Physics | 7 | Active |
| US9268636B2 | Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices | Physics | 7 | Active |
| US8693269B2 | Memory device for managing timing parameters | Physics | 7 | Active |
| US11663008B2 | Managing memory device with processor-in-memory circuit to perform memory or processing operation | Physics | 7 | Active |
| US8730710B2 | Semiconductor memory device having stacked structure including resistor-switched based logic circuit and method of manufacturing the same | Physics | 7 | Active |
| US9632856B2 | Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices | Physics | 6 | Active |
| US8477554B2 | Semiconductor memory device | Physics | 6 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.